module counter_tb; 
  reg clk, reset, enable; 
  wire [3:0] count; 
    
  counter U0 ( 
  .clk    (clk), 
  .reset  (reset), 
  .enable (enable), 
  .count  (count) 
  ); 
    
  initial begin
    clk = 0; 
    reset = 0; 
    enable = 0; 
  end 
    
  always  
    #5 clk = !clk; 
    
  initial  begin
    $dumpfile ("output/counter.vcd"); 
    $dumpvars; 
  end 
    
  initial  begin
    $display("\t\ttime,\tclk,\treset,\tenable,\tcount"); 
    $monitor("%d,\t%b,\t%b,\t%b,\t%d",$time, clk,reset,enable,count); 
  end 
    
  initial 
  #100 $finish; 
    
  //Rest of testbench code after this line
  event reset_trigger; 
  event  reset_done_trigger; 
    
  initial begin 
    forever begin 
      @ (reset_trigger); 
      @ (negedge clk); 
      reset = 1; 
      @ (negedge clk); 
      reset = 0; 
      -> reset_done_trigger; 
    end 
  end

  event terminate_sim;  
  initial begin  
  @ (terminate_sim); 
    #5 $finish; 
  end

  initial  
  begin: TEST_CASE 
    #10 -> reset_trigger; 
    @ (reset_done_trigger); 
    @ (negedge clk); 
    enable = 1; 
    repeat (10) begin 
      @ (negedge clk); 
    end 
    enable = 0; 
    #5 -> terminate_sim; 
  end
    
endmodule
